In the fabrication of semiconductor integrated circuits, metal conductor lines are used to interconnect the multiple components in device circuits on a semiconductor wafer. A general process used in the deposition of metal conductor line patterns on semiconductor wafers includes deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal conductor line pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby leaving the metal layer in the form of the masked conductor line pattern; and removing the mask layer typically using reactive plasma and chlorine gas, thereby exposing the top surface of the metal conductor lines. Typically, multiple alternating layers of electrically conductive and insulative materials are sequentially deposited on the wafer substrate, and conductive layers at different levels on the wafer may be electrically connected to each other by etching vias, or openings, in the insulative layers and filling the vias using aluminum, tungsten or other metal to establish electrical connection between the conductive layers.
Deposition of conductive layers on the wafer substrate can be carried out using any of a variety of techniques. These include oxidation, LPCVD (low-pressure chemical vapor deposition), APCVD (atmospheric-pressure chemical vapor deposition), and PECVD (plasma-enhanced chemical vapor deposition). In general, chemical vapor deposition involves reacting vapor-phase chemicals that contain the required deposition constituents with each other to form a nonvolatile film on the wafer substrate. Chemical vapor deposition is the most widely-used method of depositing films on wafer substrates in the fabrication of integrated circuits on the substrates.
Due to the ever-decreasing size of semiconductor components and the ever-increasing density of integrated circuits on a wafer, the complexity of interconnecting the components in the circuits requires that the fabrication processes used to define the metal conductor line interconnect patterns be subjected to precise dimensional control. Advances in lithography and masking techniques and dry etching processes, such as RIE (Reactive Ion Etching) and other plasma etching processes, allow production of conducting patterns with widths and spacings in the submicron range. Electrodeposition or electroplating of metals on wafer substrates has recently been identified as a promising technique for depositing conductive layers on the substrates in the manufacture of integrated circuits and flat panel displays. Such electrodeposition processes have been used to achieve deposition of the copper or other metal layer with a smooth, level or uniform top surface. Consequently, much effort is currently focused on the design of electroplating hardware and chemistry to achieve high-quality films or layers which are uniform across the entire surface of the substrates and which are capable of filling or conforming to very small device features. Copper has been found to be particularly advantageous as an electroplating metal.
Electroplated copper provides several advantages over electroplated aluminum when used in integrated circuit (IC) applications. Copper is less electrically resistive than aluminum and is thus capable of higher frequencies of operation. Furthermore, copper is more resistant to electromigration (EM) than is aluminum. This provides an overall enhancement in the reliability of semiconductor devices because circuits which have higher current densities and/or lower resistance to EM have a tendency to develop voids or open circuits in their metallic interconnects. These voids or open circuits may cause device failure or burn-in.
Electrochemical mechanical deposition (ECMD) is a technique which has been developed recently for plating a conductive material on a semiconductor wafer or workpiece surface. One goal of ECMD is to uniformly fill holes and trenches on the wafer/workpiece surface with the conductive material while maintaining the planarity of the surface. During the ECMD process, a conductive material, such as copper from a typically copper anode, is applied in holes, trenches and/or other desired areas on the wafer using an electrolyte solution in the anode assembly. The electrolyte solution flows from the anode and the copper cations from the anode are reduced to form a copper layer on the wafer.
After the electrochemical plating process, the wafer is normally subjected to an edge bead removal, or edge bevel removal (EBR), process to remove residual copper precipitate and electrolytes from the wafer. In the EBR process, the wafer is contained in an EBR chamber and subjected to a three-step cleaning process. The first step involves rinsing the wafer with deionized water to remove residual copper electrolytes from the wafer. In a second step, the edges of the wafer are rinsed with a cleaning solution, such as sulfuric acid (H2SO4), to remove copper precipitate from the wafer edge. Finally, the wafer is again rinsed with deionized water to remove the cleaning solution from the wafer. During the EBR process, the wafer is typically supported by a wafer support hoop in the EBR chamber.
A typical conventional wafer support hoop 10 is shown in FIG. 1 and includes a circular frame 12 fitted with typically at least three triangle-shaped wafer support pins 14. As shown in FIG. 1A, the wafer 16 rests on the wafer support pins 14, with the patterned surface of the wafer 16 in contact with the upper surfaces of the wafer support pins 14. One of the problems inherent in the conventional wafer support hoop 10 is that, due to the large surface area of the wafer 16 in contact with each of the wafer support pins 14, a large quantity of residual particles tend to accumulate on the wafer support pins 14. Consequently, particle-induced defects frequently form in the patterned surface of the wafer 16. For example, the particles tend to scratch or peel the wafer 16 upon inadvertent movement of the wafer 16 on the wafer support pins 14 during the EBR process, as well as upon positioning or removal of the wafer 16 on or from the wafer support pins 14. Accordingly, a new and improved wafer support for an EBR chamber is needed which minimizes or eliminates contact between the patterned surface of the wafer and the wafer support elements.
An object of the present invention is to provide a new and improved device for supporting a wafer in a process chamber.
Another object of the present invention is to provide a new and improved wafer support which prevents contamination or formation of defects on a wafer during support of the wafer in a process chamber.
Still another object of the present invention is to provide a new and improved wafer support which may be adapted for use in electroplating systems for semiconductor fabrication.
Yet another object of the present invention is to provide a new and improved wafer support which includes multiple gripping elements that engage the edges or bevels of a wafer to prevent or minimize contact of the wafer support with the patterned surface on the wafer.
A still further object of the present invention is to provide a new and improved wafer support which includes multiple gripping elements that may be moved into engagement with the edges of a wafer to support the wafer in a process chamber while substantially minimizing contact with the patterned surface on the wafer.
Yet another object of the present invention is to provide a new and improved wafer support which may include multiple wafer-gripping elements that engage the bevel or edge of a wafer at different locations on the wafer bevel or edge to support the wafer in a process chamber.